Information

Section number Title Page
48.8 Application information................................................................................................................................................1359
48.8.1 Transmit/receive data buffer operation........................................................................................................1359
48.8.2 ISO-7816 initialization sequence.................................................................................................................1360
48.8.3 Initialization sequence (non ISO-7816).......................................................................................................1362
48.8.4 Overrun (OR) flag implications...................................................................................................................1363
48.8.5 Overrun NACK considerations....................................................................................................................1364
48.8.6 Match address registers................................................................................................................................1365
48.8.7 Modem feature.............................................................................................................................................1365
48.8.8 IrDA minimum pulse width.........................................................................................................................1366
48.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1366
48.8.10 Legacy and reverse compatibility considerations........................................................................................1367
Chapter 49
Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
49.1 Introduction...................................................................................................................................................................1369
49.1.1 Features........................................................................................................................................................1369
49.1.2 Block diagram..............................................................................................................................................1369
49.1.3 Modes of operation......................................................................................................................................1370
49.2 External signals.............................................................................................................................................................1371
49.3 Memory map and register definition.............................................................................................................................1371
49.3.1 SAI Transmit Control Register (I2Sx_TCSR).............................................................................................1373
49.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................................................................................1376
49.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)................................................................................1376
49.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)................................................................................1378
49.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)................................................................................1379
49.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)................................................................................1380
49.3.7 SAI Transmit Data Register (I2Sx_TDRn)..................................................................................................1381
49.3.8 SAI Transmit FIFO Register (I2Sx_TFRn).................................................................................................1381
49.3.9 SAI Transmit Mask Register (I2Sx_TMR)..................................................................................................1382
49.3.10 SAI Receive Control Register (I2Sx_RCSR)...............................................................................................1383
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
46
Preliminary
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