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Step Action
1 Write 1b to the TCD.major.e_link bit.
2 Read back the TCD.major.e_link bit.
3 Test the TCD.major.e_link request status:
• If TCD.major.e_link = 1b, the dynamic link attempt was
successful.
• If TCD.major.e_link = 0b, the attempted dynamic link
did not succeed (the channel was already retiring).
For this request, the TCD local memory controller forces the TCD.major.e_link bit to
zero on any writes to a channel’s TCD.word7 after that channel’s TCD.done bit is set,
indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the
TCD.major.e_link bit. The TCD.done bit is cleared
automatically by the eDMA engine after a channel begins
execution.
21.5.7.3 Dynamic scatter/gather
Scatter/gather is the process of automatically loading a new TCD into a channel. When
scatter/gather is enabled and the channel has finished its major loop, a new TCD is
fetched from system memory and loaded into that channel’s descriptor location in eDMA
programmer’s model, thus replacing the current descriptor.
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
scatter/gather operation by enabling the TCD.e_sg bit at the same time the eDMA engine
is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it
would be unclear whether the actual scatter/gather request was honored before the
channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1
has the advantage of reading the major.linkch field and the e_sg bit with a single read.
For both dynamic channel linking and scatter/gather requests, the TCD local memory
controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a
channel’s TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is
complete.
NOTE
The user must clear the TCD.done bit before writing the
TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
467
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