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Section number Title Page
49.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................................1386
49.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................................1386
49.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................................1388
49.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)..................................................................................1389
49.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)..................................................................................1390
49.3.16 SAI Receive Data Register (I2Sx_RDRn)...................................................................................................1391
49.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................................1391
49.3.18 SAI Receive Mask Register (I2Sx_RMR)...................................................................................................1392
49.3.19 SAI MCLK Control Register (I2Sx_MCR).................................................................................................1392
49.3.20 SAI MCLK Divide Register (I2Sx_MDR)..................................................................................................1393
49.4 Functional description...................................................................................................................................................1394
49.4.1 SAI clocking................................................................................................................................................1394
49.4.2 SAI resets.....................................................................................................................................................1395
49.4.3 Synchronous modes.....................................................................................................................................1396
49.4.4 Frame sync configuration.............................................................................................................................1397
49.4.5 Data FIFO....................................................................................................................................................1398
49.4.6 Word mask register......................................................................................................................................1399
49.4.7 Interrupts and DMA requests.......................................................................................................................1399
Chapter 50
General-Purpose Input/Output (GPIO)
50.1 Introduction...................................................................................................................................................................1403
50.1.1 Features........................................................................................................................................................1403
50.1.2 Modes of operation......................................................................................................................................1403
50.1.3 GPIO signal descriptions.............................................................................................................................1404
50.2 Memory map and register definition.............................................................................................................................1405
50.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................1407
50.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................1407
50.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................1408
50.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................1408
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
47
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