Information

Section number Title Page
51.7 Functional description...................................................................................................................................................1427
51.7.1 Capacitance measurement............................................................................................................................1427
51.7.2 TSI measurement result...............................................................................................................................1431
51.7.3 Electrode scan unit.......................................................................................................................................1432
51.7.4 Touch detection unit.....................................................................................................................................1435
51.8 Application information................................................................................................................................................1436
51.8.1 TSI module sensitivity.................................................................................................................................1436
51.9 TSI module initialization..............................................................................................................................................1436
51.9.1 Initialization sequence..................................................................................................................................1436
Chapter 52
JTAG Controller (JTAGC)
52.1 Introduction...................................................................................................................................................................1437
52.1.1 Block diagram..............................................................................................................................................1437
52.1.2 Features........................................................................................................................................................1438
52.1.3 Modes of operation......................................................................................................................................1438
52.2 External signal description............................................................................................................................................1440
52.2.1 TCK—Test clock input................................................................................................................................1440
52.2.2 TDI—Test data input...................................................................................................................................1440
52.2.3 TDO—Test data output................................................................................................................................1440
52.2.4 TMS—Test mode select...............................................................................................................................1440
52.3 Register description......................................................................................................................................................1441
52.3.1 Instruction register.......................................................................................................................................1441
52.3.2 Bypass register.............................................................................................................................................1441
52.3.3 Device identification register.......................................................................................................................1441
52.3.4 Boundary scan register.................................................................................................................................1442
52.4 Functional description...................................................................................................................................................1443
52.4.1 JTAGC reset configuration..........................................................................................................................1443
52.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1443
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
49
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