Information

23.7.1 Watchdog Status and Control Register High
(WDOG_STCTRLH)
Address: 4005_2000h base + 0h offset = 4005_2000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
DISTESTWDO
G
BYTESEL[1:0]
TESTSEL
TESTWDOG
0
Reserved
WAITEN
STOPEN
DBGEN
ALLOWUPDAT
E
WINEN
IRQRSTEN
CLKSRC
WDOGEN
Write
Reset
0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1
WDOG_STCTRLH field descriptions
Field Description
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
DISTESTWDOG
Allows the WDOG’s functional test mode to be disabled permanently. After it is set, it can only be cleared
by a reset. It cannot be unlocked for editing after it is set.
0 WDOG functional test mode is not disabled.
1 WDOG functional test mode is disabled permanently until reset.
13–12
BYTESEL[1:0]
This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode.
00 Byte 0 selected
01 Byte 1 selected
10 Byte 2 selected
11 Byte 3 selected
11
TESTSEL
Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer.
0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for
operation and are compared for time-out against the corresponding byte of the programmed time-out
value. Select the byte through BYTESEL[1:0] for testing.
10
TESTWDOG
Puts the watchdog in the functional test mode. In this mode, the watchdog timer and the associated
compare and reset generation logic is tested for correct operation. The clock for the timer is switched from
the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the
test to be run.
9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
Reserved
This field is reserved.
7
WAITEN
Enables or disables WDOG in Wait mode.
0 WDOG is disabled in CPU Wait mode.
1 WDOG is enabled in CPU Wait mode.
6
STOPEN
Enables or disables WDOG in Stop mode.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
492
Preliminary
Freescale Semiconductor, Inc.
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