Information

WDOG_STCTRLH field descriptions (continued)
Field Description
0 WDOG is disabled in CPU Stop mode.
1 WDOG is enabled in CPU Stop mode.
5
DBGEN
Enables or disables WDOG in Debug mode.
0 WDOG is disabled in CPU Debug mode.
1 WDOG is enabled in CPU Debug mode.
4
ALLOWUPDATE
Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window
(WCT) closes, through unlock sequence.
0 No further updates allowed to WDOG write-once registers.
1 WDOG write-once registers can be unlocked for updating.
3
WINEN
Enables Windowing mode.
0 Windowing mode is disabled.
1 Windowing mode is enabled.
2
IRQRSTEN
Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed
to updating after WCT.
0 WDOG time-out generates reset only.
1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
1
CLKSRC
Selects clock source for the WDOG timer and other internal timing operations.
0 WDOG clock sourced from LPO .
1 WDOG clock sourced from alternate clock source.
0
WDOGEN
Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset
state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit
must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
0 WDOG is disabled.
1 WDOG is enabled.
23.7.2 Watchdog Status and Control Register Low
(WDOG_STCTRLL)
Address: 4005_2000h base + 2h offset = 4005_2002h
Bit 15 14 13 12 11 10 9 8
Read
INTFLG Reserved
Write
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
Read
Reserved
Write
Reset
0 0 0 0 0 0 0 1
Chapter 23 Watchdog Timer (WDOG)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
493
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