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23.7.5 Watchdog Window Register High (WDOG_WINH)
NOTE
You must set the Window Register value lower than the Time-
out Value Register.
Address: 4005_2000h base + 8h offset = 4005_2008h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WINHIGH
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDOG_WINH field descriptions
Field Description
15–0
WINHIGH
Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is
defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when
the timer has reached a value greater than or equal to this window length. A refresh outside this window
resets the system or if IRQRSTEN is set, it interrupts and then resets the system.
23.7.6 Watchdog Window Register Low (WDOG_WINL)
NOTE
You must set the Window Register value lower than the Time-
out Value Register.
Address: 4005_2000h base + Ah offset = 4005_200Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WINLOW
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
WDOG_WINL field descriptions
Field Description
15–0
WINLOW
Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is
defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed
only when the timer reaches a value greater than or equal to this window length value. A refresh outside of
this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system.
Chapter 23 Watchdog Timer (WDOG)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
495
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