Information

WDOG_TMROUTH field descriptions
Field Description
15–0
TIMEROUTHIGH
Shows the value of the upper 16 bits of the watchdog timer.
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)
During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the
watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3
bus clock cycles will occur before the WDOG_TIMER_OUT starts following the
watchdog timer.
Address: 4005_2000h base + 12h offset = 4005_2012h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
TIMEROUTLOW
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDOG_TMROUTL field descriptions
Field Description
15–0
TIMEROUTLOW
Shows the value of the lower 16 bits of the watchdog timer.
23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)
Address: 4005_2000h base + 14h offset = 4005_2014h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
RSTCNT
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDOG_RSTCNT field descriptions
Field Description
15–0
RSTCNT
Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing
1 to the bit to be cleared enables you to clear the contents of this register.
Chapter 23 Watchdog Timer (WDOG)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
497
General Business Information