Information

23.7.12 Watchdog Prescaler register (WDOG_PRESC)
Address: 4005_2000h base + 16h offset = 4005_2016h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
PRESCVAL
0
Write
Reset
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
WDOG_PRESC field descriptions
Field Description
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
PRESCVAL
3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG
clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK.
7–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23.8 Watchdog operation with 8-bit access
23.8.1 General guideline
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is
to access both the bytes of a register, place the two 8-bit accesses one after the other in
your code.
23.8.2 Refresh and unlock operations with 8-bit access
One exception condition that generates a reset to the system is the write of any value
other than those required for a legal refresh/update sequence to the respective refresh and
unlock registers.
For an 8-bit access to these registers, writing a correct value requires at least two bus
clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the
system is reset even if the intention is to write a correct value to the refresh/unlock
register. Keeping this in mind, the exception condition for 8-bit accesses is slightly
modified.
Watchdog operation with 8-bit access
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
498
Preliminary
Freescale Semiconductor, Inc.
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