Information

Chapter 27
Flash Memory Controller (FMC)
27.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The Flash Memory Controller (FMC) is a memory acceleration unit that provides:
• an interface between the device and the dual-bank nonvolatile memory. Bank 0
consists of program flash memory, and bank 1 consists of FlexNVM.
• buffers that can accelerate flash memory transfers.
27.1.1 Overview
The Flash Memory Controller manages the interface between the device and the dual-
bank flash memory. The FMC receives status information detailing the configuration of
the memory and uses this information to ensure a proper interface. The following table
shows the supported read/write operations.
Flash memory type Read Write
Program flash memory 8-bit, 16-bit, and 32-bit reads —
1
FlexNVM used as Data flash memory 8-bit, 16-bit, and 32-bit reads —
1
FlexNVM and FlexRAM used as
EEPROM
8-bit, 16-bit, and 32-bit reads 8-bit, 16-bit, and 32-bit writes
1. A write operation to program flash memory or to FlexNVM used as data flash memory results in a bus error.
In addition, for bank 0, the FMC provides three separate mechanisms for accelerating the
interface between the device and the flash memory. A 64-bit speculation buffer can
prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache and a
single-entry 64-bit buffer can store previously accessed flash memory data for quick
access times.
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
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