Information

FMC_PFB1CR field descriptions
Field Description
31–28
B1RWSC[3:0]
Bank 1 Read Wait State Control
This read-only field defines the number of wait states required to access the bank 1 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
27–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–17
B1MW[1:0]
Bank 1 Memory Width
This read-only field defines the width of the bank 1 memory.
00 32 bits
01 64 bits
10 Reserved
11 Reserved
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)
The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and
the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
This section represents tag/vld information for all sets in the indicated way.
Address: 4001_F000h base + 100h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
tag[18:6]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
tag[18:6]
0
valid
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
570
Preliminary
Freescale Semiconductor, Inc.
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