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• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n
nvmcycd
— data flash cycling endurance
Figure 28-31. EEPROM backup writes to FlexRAM
28.4.3 Interrupts
The flash memory module can generate interrupt requests to the MCU upon the
occurrence of various flash events. These interrupt events and their associated status and
control bits are shown in the following table.
Table 28-30. Flash Interrupt Sources
Flash Event Readable
Status Bit
Interrupt
Enable Bit
Flash Command Complete FSTAT[CCIF] FCNFG[CCIE]
Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE]
Chapter 28 Flash Memory Module (FTFL)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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