Information

Bus name Description

System bus The system bus is connected to a separate master port on the crossbar. In addition, the

system bus is tightly coupled to the upper half system RAM (SRAM_U).

Private peripheral (PPB) bus The PPB provides access to these modules:

• ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table

• Freescale Miscellaneous Control Module (MCM)

3.2.1.2 System Tick Timer

The System Tick Timer's clock source is always the core clock, FCLK. This results in the

following:

• The CLKSOURCE bit in SysTick Control and Status register is always set to select

the core clock.

• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the

SysTick Calibration Value Register is always zero.

• The NOREF bit in SysTick Calibration Value Register is always set, implying that

FCLK is the only available source of reference timing.

3.2.1.3 Debug facilities

This device has extensive debug capabilities including run control and tracing

capabilities. The standard ARM debug port that supports JTAG and SWD interfaces.

Also the cJTAG interface is supported on this device.

3.2.1.4 Core privilege levels

The ARM documentation uses different terms than this document to distinguish between

privilege levels.

If you see this term... it also means this term...

Privileged Supervisor

Unprivileged or user User

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration

This section summarizes how the module has been configured in the chip. Full

documentation for this module is provided by ARM and can be found at www.arm.com.

Chapter 3 Chip Configuration

K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

Freescale Semiconductor, Inc.

Preliminary

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