Information

29.1.2 Features
FlexBus offers the following features:
• Six independent, user-programmable chip-select signals (FB_CS5 –FB_CS0)
• 8-bit, 16-bit, and 32-bit port sizes with configuration for multiplexed or
nonmultiplexed address and data buses
• 8-bit, 16-bit, 32-bit, and 16-byte transfers
• Programmable burst and burst-inhibited transfers selectable for each chip-select and
transfer direction
• Programmable address-setup time with respect to the assertion of a chip-select
• Programmable address-hold time with respect to the deassertion of a chip-select and
transfer direction
• Extended address latch enable option to assist with glueless connections to
synchronous and asynchronous memory devices
29.2 Signal descriptions
This table describes the external signals involved in data-transfer operations.
NOTE
Not all of the following signals may be available on a particular
device. See the Chip Configuration details for information on
which signals are available.
Table 29-1. FlexBus signal descriptions
Signal I/O Function
FB_A31–FB_A0 O Address Bus
When FlexBus is used in a nonmultiplexed configuration, this is the address bus. When
FlexBus is used in a multiplexed configuration, this bus is not used.
FB_D31–FB_D0 I/O Data Bus—During the first cycle, this bus drives the upper address byte, addr[31:24].
When FlexBus is used in a nonmultiplexed configuration, this is the data bus, FB_D.
When FlexBus is used in a multiplexed configuration, this is the address and data bus,
FB_AD.
The number of byte lanes carrying the data is determined by the port size associated
with the matching chip-select.
When FlexBus is used in a multiplexed configuration, the full 32-bit address is driven on
the first clock of a bus cycle (address phase). After the first clock, the data is driven on
the bus (data phase). During the data phase, the address is driven on the pins not used
for data. For example, in 16-bit mode, the lower address is driven on FB_AD15–
FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0.
Table continues on the next page...
Signal descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
644
Preliminary
Freescale Semiconductor, Inc.
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