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Table 29-1. FlexBus signal descriptions (continued)
Signal I/O Function
FB_CS5–FB_CS0 O General Purpose Chip-Selects—Indicate which external memory or peripheral is
selected. A particular chip-select is asserted when the transfer address is within the
external memory's or peripheral's address space, as defined in CSAR[BA] and
CSMR[BAM].
FB_BE_31_24
FB_BE_23_16
FB_BE_15_8
FB_BE_7_0
O Byte Enables—Indicate that data is to be latched or driven onto a specific byte lane of
the data bus. CSCR[BEM] determines if these signals are asserted on reads and writes
or on writes only.
For external SRAM or flash devices, the FB_BE outputs should be connected to
individual byte strobe signals.
FB_OE O Output Enable—Sent to the external memory or peripheral to enable a read transfer.
This signal is asserted during read accesses only when a chip-select matches the
current address decode.
FB_R/W O Read/Write—Indicates whether the current bus operation is a read operation (FB_R/W
high) or a write operation (FB_R/W low).
FB_TS O Transfer Start—Indicates that the chip has begun a bus transaction and that the
address and attributes are valid.
An inverted FB_TS is available as an address latch enable (FB_ALE), which indicates
when the address is being driven on the FB_AD bus.
FB_TS/FB_ALE is asserted for one bus clock cycle.
The chip can extend this signal until the first positive clock edge after
FB_CS asserts.
See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable.
FB_ALE O Address Latch Enable—Indicates when the address is being driven on the FB_A bus
(inverse of FB_TS).
Table continues on the next page...
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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