Information

FB_CSMRn field descriptions (continued)
Field Description
NOTE: At reset, no chip-select other than FB_CS0 can be used until CSMR0[V] is 1b. Afterward, the
FB_CS [5:0] signals function as programmed.
0 Chip-select is invalid.
1 Chip-select is valid.
29.3.3 Chip Select Control Register (FB_CSCRn)
Controls the auto-acknowledge, address setup and hold times, port size, burst capability,
and number of wait states for the associated chip select.
NOTE
To support the global chip-select (
FB_CS0 ), the CSCR0 reset
values differ from the other CSCRs. The reset value of CSCR0
is as follows:
• Bits 31–24 are 0b
• Bit 23–3 are chip-dependent
• Bits 3–0 are 0b
See the chip configuration details for your particular chip for
information on the exact CSCR0 reset value.
Address: 4000_C000h base + 8h offset + (12d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SWS
0
SWSEN
EXTS ASET RDAH WRAH
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WS BLS AA PS BEM BSTR
BSTW
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FB_CSCRn field descriptions
Field Description
31–26
SWS
Secondary Wait States
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
650
Preliminary
Freescale Semiconductor, Inc.
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