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29.4.2 Address comparison
When a bus cycle is routed to FlexBus, FlexBus compares the transfer address to the base
address and base address mask. This table describes how FlexBus decides to assert a
chip-select and complete the bus cycle based on the address comparison.
When the transfer address Then FlexBus
Matches one address register
configuration
Asserts the appropriate chip-select, generating a FlexBus bus cycle as defined in the
appropriate CSCR.
If CSMR[WP] is set and a write access is performed, FlexBus terminates the internal
bus cycle with a bus error, does not assert a chip-select, and does not perform an
external bus cycle.
Does not match a address register
configuration
Terminates the transfer with a bus error response, does not assert a chip-select, and
does not perform a FlexBus cycle.
Matches more than one address
register configuration
Terminates the transfer with a bus error response, does not assert a chip-select, and
does not perform a FlexBus cycle.
29.4.3 Address driven on address bus
FlexBus always drives a 32-bit address on the FB_AD bus regardless of the external
memory's or peripheral's address size.
29.4.4 Connecting address/data lines
The external device must connect its address and data lines as follows:
• Address lines
• FB_AD from FB_AD0 upward
• Data lines
• If CSCR[BLS] = 0, FB_AD from FB_AD31 downward
• If CSCR[BLS] = 1, FB_AD from FB_AD0 upward
29.4.5 Bit ordering
No bit ordering is required when connecting address and data lines to the FB_AD bus.
For example, a full 16-bit address/16-bit data device connects its addr15–addr0 to
FB_AD16–FB_AD1 and data15–data0 to FB_AD31–FB_AD16. See Data-byte
alignment and physical connections for a graphical connection.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
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