Information

29.4.6 Data transfer signals
Data transfers between FlexBus and the external memory or peripheral involve these
signals:
• Address/data bus (FB_AD31–FB_AD0 )
• Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_R/W, FB_BEn)
• Attribute signals (FB_TBST, FB_TSIZ1–FB_TSIZ0)
29.4.7 Signal transitions
These signals change on the rising edge of the FlexBus clock (FB_CLK):
• Address
• Write data
• FB_TS/FB_ALE
• FB_CSn
• All attribute signals
FlexBus latches the read data on the rising edge of the clock.
29.4.8 Data-byte alignment and physical connections
The device aligns data transfers in FlexBus byte lanes with the number of lanes
depending on the data port width.
The following figure shows the byte lanes that external memory or peripheral connects to
and the sequential transfers of a 32-bit transfer for the supported port sizes when byte
lane shift is disabled. For example, an 8-bit memory connects to the single lane
FB_AD31–FB_AD24 (
FB_BE_31_24). A 32-bit transfer through this 8-bit port takes
four transfers, starting with the LSB to the MSB. A 32-bit transfer through a 32-bit port
requires one transfer on each four-byte lane.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
656
Preliminary
Freescale Semiconductor, Inc.
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