Information

32-Bit Port
Memory
16-Bit Port
Memory
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
Byte 1 Byte 0
Byte 3 Byte 2
Byte 3 Byte 2 Byte 1 Byte 0
Driven with
address values
Driven with
address values
External
Data Bus
Byte Select
FB_D31–
FB_D24
FB_D23–
FB_D16
FB_D15–
FB_D8
FB_D7–
FB_D0
FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0
Figure 29-23. Connections for external memory port sizes (CSCRn[BLS] = 0)
The following figure shows the byte lanes that external memory or peripheral connects to
and the sequential transfers of a 32-bit transfer for the supported port sizes when byte
lane shift is enabled.
32-Bit Port
Memory
16-Bit Port
Memory
8-Bit Port
Memory
Byte 3 Byte 2
Byte 1 Byte 0
Driven with
address values
Driven with
address values
Byte 1 Byte 0
Byte 3 Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
External Data Bus
Byte Select
FB_AD[31:24]
FB_AD[23:16]
FB_AD15:8]
FB_AD[7:0]
FB_BE31_24 FB_BE23_16 FB_BE15_8 FB_BE7_0
FB_BE23_16FB_BE31_24
FB_BE31_24
Figure 29-24. Connections for external memory port sizes (CSCRn[BLS] = 1)
29.4.9 Address/data bus multiplexing
FlexBus supports a single 32-bit wide multiplexed address and data bus (FB_AD31–
FB_AD0). FlexBus always drives the full 32-bit address on the first clock of a bus cycle.
During the data phase, the FB_AD31– FB_AD0 lines used for data are determined by the
programmed port size and BLS setting for the corresponding chip-select. FlexBus
continues to drive the address on any FB_AD31– FB_AD0 lines not used for data.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
657
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