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The address and data busses are muxed between the FlexBus
and another module. At the end of the read bus cycles the
address signals are indeterminate.
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-26. Basic Read-Bus Cycle
29.4.11.2 Basic Write Bus Cycle
During a write cycle, the device sends data to memory or to a peripheral device. The
following figure shows the write cycle flowchart.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
661
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