Information

Add
Data
TSIZ = 00
AA=1
AA=0
AA=1
AA=0
Data
Data Data
TSIZ = 01
Add+3Add+2
Add+1
Add+1 Add+2 Add+3
Address
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TBST
FB_TSIZ[1:0]
29.4.12.6 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state)
The following figure illustrates another read burst transfer, but in this case a wait state is
added between individual beats.
Note
CSCRn[WS] determines the number of wait states in the first
beat. However, for subsequent beats, the CSCRn[WS] (or
CSCRn[SWS] if CSCRn[SWSEN] = 1b) determines the
number of wait states.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
682
Preliminary
Freescale Semiconductor, Inc.
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