Information

Address
Address Data
TSIZ=11
AA=1
AA=0
AA=1
AA=0
Data Data Data
Add+1 Add+2 Add+3
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
29.4.12.9 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and
hold)
The following figure shows a write cycle with one clock of address setup and address
hold.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
685
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