Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-44. Read-Bus Cycle with CSCRn[EXTS] = 1 (One Wait State)
29.4.14 Bus errors
These types of accesses cause a transfer to terminate with a bus error:
• A write to a write-protected address range
• An access whose address is not in a range covered by a chip-select
• An access whose address is in a range covered by more than one chip-selects
• A write to a reserved address in the memory map
• A write to a reserved field in the CSPMCR
• Any FlexBus accesses when FlexBus is secure
If the auto-acknowledge feature is disabled (CSCR[AA] is 0) for an address that
generates an error, the transfer can be terminated by asserting FB_TA. If the processor
must manage a bus error differently, asserting an interrupt to the core along with FB_TA
when the bus error occurs can invoke an interrupt handler.
The device can hang if FlexBus is configured for external termination and the CSPMCR
is not configured for
FB_TA.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
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