Information
ADCx_SC1n field descriptions (continued)
Field Description
01100 When DIFF=0, AD12 is selected as input ; when DIFF=1, it is reserved .
01101 When DIFF=0, AD13 is selected as input ; when DIFF=1, it is reserved .
01110 When DIFF=0, AD14 is selected as input ; when DIFF=1, it is reserved .
01111 When DIFF=0, AD15 is selected as input ; when DIFF=1, it is reserved .
10000 When DIFF=0, AD16 is selected as input ; when DIFF=1, it is reserved .
10001 When DIFF=0, AD17 is selected as input ; when DIFF=1, it is reserved .
10010 When DIFF=0, AD18 is selected as input ; when DIFF=1, it is reserved .
10011 When DIFF=0, AD19 is selected as input ; when DIFF=1, it is reserved .
10100 When DIFF=0, AD20 is selected as input ; when DIFF=1, it is reserved .
10101 When DIFF=0, AD21 is selected as input ; when DIFF=1, it is reserved .
10110 When DIFF=0, AD22 is selected as input ; when DIFF=1, it is reserved .
10111 When DIFF=0, AD23 is selected as input ; when DIFF=1, it is reserved .
11000 Reserved.
11001 Reserved.
11010 When DIFF=0, Temp sensor (single-ended) is selected as input ; when DIFF=1, Temp sensor
(differential) is selected as input .
11011 When DIFF=0,Bandgap (single-ended) is selected as input ; when DIFF=1, Bandgap (differential)
is selected as input .
11100 Reserved.
11101 V is selected as input . Voltage reference selected is determined by SC2[REFSEL]. When
DIFF=0,
REFSH
; when DIFF=1, -V
REFSH
(differential) is selected as input
11110 V is selected as input . Voltage reference selected is determined by SC2[REFSEL]. When
DIFF=0,
REFSL
; when DIFF=1, it is reserved
11111 Module disabled.
32.3.2 ADC Configuration Register 1 (ADCx_CFG1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock
divide, and configuration for low power or long sample time.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADLPC
ADIV
ADLSMP
MODE ADICLK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
720
Preliminary
Freescale Semiconductor, Inc.
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