Information

32.3.18 ADC PGA Register (ADCx_PGA)
Address: Base address + 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
PGAEN
0
PGALPb
PGAG
W
0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_PGA field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
PGAEN
PGA Enable
0 PGA disabled.
1 PGA enabled.
22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21
Reserved
This field is reserved.
20
PGALPb
PGA Low-Power Mode Control
0 PGA runs in Low-Power mode.
1 PGA runs in Normal Power mode.
19–16
PGAG
PGA Gain Setting
PGA gain = 2^(PGAG)
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 Reserved
1000 Reserved
1001 Reserved
Table continues on the next page...
Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
734
Preliminary
Freescale Semiconductor, Inc.
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