Information

32.3.20 ADC Minus-Side General Calibration Value Register
(ADCx_CLMS)
For more information, see CLMD register description.
Address: Base address + 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLMS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLMS field descriptions
Field Description
31–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–0
CLMS
Calibration Value
32.3.21 ADC Minus-Side General Calibration Value Register
(ADCx_CLM4)
For more information, see CLMD register description.
Address: Base address + 5Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM4
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
ADCx_CLM4 field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–0
CLM4
Calibration Value
Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
736
Preliminary
Freescale Semiconductor, Inc.
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