Information

32.3.24 ADC Minus-Side General Calibration Value Register
(ADCx_CLM1)
For more information, see CLMD register description.
Address: Base address + 68h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
ADCx_CLM1 field descriptions
Field Description
31–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–0
CLM1
Calibration Value
32.3.25 ADC Minus-Side General Calibration Value Register
(ADCx_CLM0)
For more information, see CLMD register description.
Address: Base address + 6Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLM0 field descriptions
Field Description
31–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–0
CLM0
Calibration Value
32.4 Functional description
The ADC module is disabled during reset, in Low-Power Stop mode, or when
SC1n[ADCH] are all high; see the power management information for details. The
module is idle when a conversion has completed and another conversion has not been
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
738
Preliminary
Freescale Semiconductor, Inc.
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