Information

32.4.2 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module. This
clock source is then divided by a configurable value to generate the input clock ADCK,
to the module. The clock is selected from one of the following sources by means of
CFG1[ADICLK].
• Bus clock. This is the default selection following reset.
• Bus clock divided by two. For higher bus clock rates, this allows a maximum divide-
by-16 of the bus clock using CFG1[ADIV].
• ALTCLK: As defined for this MCU. See the chip configuration information.
• Asynchronous clock (ADACK): This clock is generated from a clock source within
the ADC module. When the ADACK clock source is selected, it is not required to be
active prior to conversion start. When it is selected and it is not active prior to a
conversion start CFG2[ADACKEN]=0, ADACK is activated at the start of a
conversion and deactivated when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated. To avoid the
conversion time variability and latency associated with the ADACK clock startup, set
CFG2[ADACKEN]=1 and wait the worst-case startup time of 5 µs prior to initiating
any conversions using the ADACK clock source. Conversions are possible using
ADACK as the input clock source while the MCU is in Normal Stop mode. See
Power Control for more information.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC may not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1,
2, 4, or 8.
32.4.3 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the
reference voltage (V
REFSH
and V
REFSL
) used for conversions. Each pair contains a
positive reference that must be between the minimum Ref Voltage High and V
DDA
, and a
ground reference that must be at the same potential as V
SSA
. The two pairs are external
(V
REFH
and V
REFL
) and alternate (V
ALTH
and V
ALTL
). These voltage references are
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
740
Preliminary
Freescale Semiconductor, Inc.
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