Information

Table 32-107. Single or first continuous time adder (SFCAdder) (continued)
CFG1[AD
LSMP]
CFG2[AD
ACKEN]
CFG1[ADICLK] Single or first continuous time adder (SFCAdder)
0 0 11 5 μs + 5 ADCK cycles + 5 bus clock cycles
1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 μs prior to the conversion is initiated.
Table 32-108. Average number factor (AverageNum)
SC3[AVGE] SC3[AVGS] Average number factor (AverageNum)
0 xx 1
1 00 4
1 01 8
1 10 16
1 11 32
Table 32-109. Base conversion time (BCT)
Mode Base conversion time (BCT)
8b single-ended 17 ADCK cycles
9b differential 27 ADCK cycles
10b single-ended 20 ADCK cycles
11b differential 30 ADCK cycles
12b single-ended 20 ADCK cycles
13b differential 30 ADCK cycles
16b single-ended 25 ADCK cycles
16b differential 34 ADCK cycles
Table 32-110. Long sample time adder (LSTAdder)
CFG1[ADLSMP] CFG2[ADLSTS]
Long sample time adder
(LSTAdder)
0 xx 0 ADCK cycles
1 00 20 ADCK cycles
1 01 12 ADCK cycles
1 10 6 ADCK cycles
1 11 2 ADCK cycles
Table 32-111. High-speed conversion time adder (HSCAdder)
CFG2[ADHSC] High-speed conversion time adder (HSCAdder)
0 0 ADCK cycles
1 2 ADCK cycles
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
746
Preliminary
Freescale Semiconductor, Inc.
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