Information

Note
The ADCK frequency must be between f
ADCK
minimum and
f
ADCK
maximum to meet ADC specifications.
32.4.5.6 Conversion time examples
The following examples use Figure 32-95 and the information provided in Table 32-107
through Table 32-111.
32.4.5.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is:
• 10-bit mode, with the bus clock selected as the input clock source
• The input clock divide-by-1 ratio selected
• Bus frequency of 8 MHz
• Long sample time disabled
• High-speed conversion disabled
The conversion time for a single conversion is calculated by using Figure 32-95 and the
information provided in Table 32-107 through Table 32-111. The table below list the
variables of Figure 32-95.
Table 32-112. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting
conversion time is 3.75 µs.
32.4.5.6.2 Long conversion time configuration
A configuration for long ADC conversion is:
• 16-bit Differential mode with the bus clock selected as the input clock source
• The input clock divide-by-8 ratio selected
• Bus frequency of 8 MHz
• Long sample time enabled
Chapter 32 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
747
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