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• Configured for longest adder
• High-speed conversion disabled
• Average enabled for 32 conversions
The conversion time for this conversion is calculated by using Figure 32-95 and the
information provided in Table 32-107 through Table 32-111. The following table lists the
variables of the Figure 32-95.
Table 32-113. Typical conversion time
Variable Time
SFCAdder 3 ADCK cycles + 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting
conversion time is 57.625 µs, that is, AverageNum. This results in a total conversion time
of 1.844 ms.
32.4.5.6.3 Short conversion time configuration
A configuration for short ADC conversion is:
• 8-bit Single-Ended mode with the bus clock selected as the input clock source
• The input clock divide-by-1 ratio selected
• Bus frequency of 20 MHz
• Long sample time disabled
• High-speed conversion enabled
The conversion time for this conversion is calculated by using Figure 32-95 and the
information provided in Table 32-107 through Table 32-111. The table below list the
variables of Figure 32-95.
Table 32-114. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
AverageNum 1
BCT 17 ADCK cycles
LSTAdder 0 ADCK cycles
HSCAdder 2
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
748
Preliminary
Freescale Semiconductor, Inc.
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