Information

3.3.6.2 Crossbar Switch Slave Assignments
The slaves connected to the crossbar switch are assigned as follows:
Slave module Slave port number
Flash memory controller 0
SRAM backdoor 1
Peripheral bridge 0
1
2
Peripheral bridge 1/GPIO
1
3
FlexBus 4
1. See System memory map for access restrictions.
3.3.6.3 PRS register reset values
The AXBS_PRSn registers reset to 0000_3210h.
3.3.7 Peripheral Bridge Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Figure 3-10. Peripheral bridge configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
Peripheral bridge (AIPS-Lite)
System memory map System memory map
Clocking Clock Distribution
Crossbar switch Crossbar switch Crossbar switch
3.3.7.1 Number of peripheral bridges
This device contains two identical peripheral bridges.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
77
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