Information

• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which is crossing clock domain boundaries,
must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
33.7 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 33.7.1/770
4007_3001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h 33.7.2/771
4007_3002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h 33.7.3/773
4007_3003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h 33.7.4/773
4007_3004 DAC Control Register (CMP0_DACCR) 8 R/W 00h 33.7.5/774
4007_3005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h 33.7.6/775
4007_3008 CMP Control Register 0 (CMP1_CR0) 8 R/W 00h 33.7.1/770
4007_3009 CMP Control Register 1 (CMP1_CR1) 8 R/W 00h 33.7.2/771
4007_300A CMP Filter Period Register (CMP1_FPR) 8 R/W 00h 33.7.3/773
4007_300B CMP Status and Control Register (CMP1_SCR) 8 R/W 00h 33.7.4/773
4007_300C DAC Control Register (CMP1_DACCR) 8 R/W 00h 33.7.5/774
4007_300D MUX Control Register (CMP1_MUXCR) 8 R/W 00h 33.7.6/775
4007_3010 CMP Control Register 0 (CMP2_CR0) 8 R/W 00h 33.7.1/770
4007_3011 CMP Control Register 1 (CMP2_CR1) 8 R/W 00h 33.7.2/771
4007_3012 CMP Filter Period Register (CMP2_FPR) 8 R/W 00h 33.7.3/773
4007_3013 CMP Status and Control Register (CMP2_SCR) 8 R/W 00h 33.7.4/773
4007_3014 DAC Control Register (CMP2_DACCR) 8 R/W 00h 33.7.5/774
4007_3015 MUX Control Register (CMP2_MUXCR) 8 R/W 00h 33.7.6/775
33.7.1 CMP Control Register 0 (CMPx_CR0)
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset
0 0 0 0 0 0 0 0
Memory map/register definitions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
770
Preliminary
Freescale Semiconductor, Inc.
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