Information

3.3.7.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot
assignment for each module.
3.3.7.3 MPRA register
Each of the two peripheral bridges supports up to 8 crossbar switch masters, each
assigned to a MPROTx field in the MPRA register. However, fewer are supported on this
device. See Crossbar switch for details of the master port assignments for this device.
3.3.7.4 AIPS_Lite MPRA register reset value
• AIPSx_MPRA reset value is 0x7770_0000
Therefore, masters 0, 1, and 2 are trusted bus masters after reset.
3.3.7.5 PACR registers
Each of the two peripheral bridges support up to 128 peripherals each assigned to an
PACRx field within the PACRA-PACRP registers. However, fewer peripherals are
supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of
the peripheral slot assignments for this device. Unused PACRx fields are reserved.
3.3.7.6 AIPS_Lite PACRE-P register reset values
The AIPSx_PACRE-P reset values depend on if the module is available on your
particular device. For each populated slot in slots 32-127 in Peripheral Bridge 0 (AIPS-
Lite 0) Memory Map and Peripheral Bridge 1 (AIPS-Lite 1) Memory Map, the
corresponding module's PACR[32:127] field resets to 0x4.
3.3.8 DMA request multiplexer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
System modules
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
78
Preliminary
Freescale Semiconductor, Inc.
General Business Information