Information

DACx_DATnL field descriptions
Field Description
7–0
DATA[7:0]
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula: V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.
34.4.2 DAC Data High Register (DACx_DATH)
Address: 400C_C000h base + 1h offset = 400C_C001h
Bit 7 6 5 4 3 2 1 0
Read 0
DATA[11:8]
Write
Reset
0 0 0 0 0 0 0 0
DACx_DATnH field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
DATA[11:8]
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
34.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset,
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only
when the data buffer status is changed.
Address: 400C_C000h base + 20h offset = 400C_C020h
Bit 7 6 5 4 3 2 1 0
Read 0 DACBFWM
F
DACBFRPT
F
DACBFRPB
F
Write
Reset
0 0 0 0 0 0 1 0
DACx_SR field descriptions
Field Description
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
DACBFWMF
DAC Buffer Watermark Flag
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
796
Preliminary
Freescale Semiconductor, Inc.
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