Information

PDB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h 36.3.1/817
4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh 36.3.2/819
4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h 36.3.3/820
4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh 36.3.4/820
4003_6010 Channel n Control Register 1 (PDB0_CH0C1) 32 R/W 0000_0000h 36.3.5/821
4003_6014 Channel n Status Register (PDB0_CH0S) 32 w1c 0000_0000h 36.3.6/822
4003_6018 Channel n Delay 0 Register (PDB0_CH0DLY0) 32 R/W 0000_0000h 36.3.7/822
4003_601C Channel n Delay 1 Register (PDB0_CH0DLY1) 32 R/W 0000_0000h 36.3.8/823
4003_6038 Channel n Control Register 1 (PDB0_CH1C1) 32 R/W 0000_0000h 36.3.5/821
4003_603C Channel n Status Register (PDB0_CH1S) 32 w1c 0000_0000h 36.3.6/822
4003_6040 Channel n Delay 0 Register (PDB0_CH1DLY0) 32 R/W 0000_0000h 36.3.7/822
4003_6044 Channel n Delay 1 Register (PDB0_CH1DLY1) 32 R/W 0000_0000h 36.3.8/823
4003_6150 DAC Interval Trigger n Control Register (PDB0_DACINTC0) 32 R/W 0000_0000h 36.3.9/823
4003_6154 DAC Interval n Register (PDB0_DACINT0) 32 R/W 0000_0000h
36.3.10/
824
4003_6190 Pulse-Out n Enable Register (PDB0_POEN) 32 R/W 0000_0000h
36.3.11/
824
4003_6194 Pulse-Out n Delay Register (PDB0_PO0DLY) 32 R/W 0000_0000h
36.3.12/
825
4003_6198 Pulse-Out n Delay Register (PDB0_PO1DLY) 32 R/W 0000_0000h
36.3.12/
825
4003_619C Pulse-Out n Delay Register (PDB0_PO2DLY) 32 R/W 0000_0000h
36.3.12/
825
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
816
Preliminary
Freescale Semiconductor, Inc.
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