Information

PDBx_IDLY field descriptions (continued)
Field Description
equal to the IDLY. Reading these bits returns the value of internal register that is effective for the current
cycle of the PDB.
36.3.5 Channel n Control Register 1 (PDBx_CHnC1)
Each PDB channel has one Control Register, CHnC1. The bits in this register control the
functionality of each PDB channel operation.
Address: 4003_6000h base + 10h offset + (40d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
BB TOS EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnC1 field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
BB
PDB Channel Pre-Trigger Back-to-Back Operation Enable
These bits enable the PDB ADC pre-trigger operation as back-to-back mode. Only lower M pre-trigger bits
are implemented in this MCU. Back-to-back operation enables the ADC conversions complete to trigger
the next PDB channel pre-trigger and trigger output, so that the ADC conversions can be triggered on next
set of configuration and results registers. Application code must only enable the back-to-back operation of
the PDB pre-triggers at the leading of the back-to-back connection chain.
0 PDB channel's corresponding pre-trigger back-to-back operation disabled.
1 PDB channel's corresponding pre-trigger back-to-back operation enabled.
15–8
TOS
PDB Channel Pre-Trigger Output Select
These bits select the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral
clock cycle after a rising edge is detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.
1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register
and one peripheral clock cycle after a rising edge is detected on selected trigger input source or
software trigger is selected and SETRIG is written with 1.
7–0
EN
PDB Channel Pre-Trigger Enable
These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0 PDB channel's corresponding pre-trigger disabled.
1 PDB channel's corresponding pre-trigger enabled.
Chapter 36 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
821
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