Information

PDBx_DACINTCn field descriptions (continued)
Field Description
0
TOE
DAC Interval Trigger Enable
This bit enables the DAC interval trigger.
0 DAC interval trigger disabled.
1 DAC interval trigger enabled.
36.3.10 DAC Interval n Register (PDBx_DACINTn)
Address: 4003_6000h base + 154h offset + (8d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTn field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
INT
DAC Interval
These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update
when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal
register that is effective for the current PDB cycle.
36.3.11 Pulse-Out n Enable Register (PDBx_POEN)
Address: 4003_6000h base + 190h offset = 4003_6190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
POEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POEN field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
POEN
PDB Pulse-Out Enable
These bits enable the pulse output. Only lower Y bits are implemented in this MCU.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
824
Preliminary
Freescale Semiconductor, Inc.
General Business Information