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• Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) +
2 peripheral clock cycles
• Add one additional peripheral clock cycle to determine the time at which the channel
trigger output change.
Each channel is associated with one ADC block. PDB channel n pre-trigger outputs 0 to
M and trigger output is connected to ADC hardware trigger select and hardware trigger
inputs. The pre-triggers are used to precondition the ADC block prior to the actual
trigger. The ADC contains M sets of configuration and result registers, allowing it to
operate in a ping-pong fashion, alternating conversions between M different analog
sources. The pre-trigger outputs are used to specify which signal will be sampled next.
When pre-trigger m is asserted, the ADC conversion is triggered with set m of the
configuration and result registers.
The waveforms shown in the following diagram illustrate the pre-trigger and trigger
outputs of PDB channel n. The delays can be independently set via the CHnDLYm
registers. And the pre-triggers can be enabled or disabled in CHnC1[EN[m]].
Trigger input event
Ch n pre-trigger 0
Ch n pre-trigger 1
Ch n pre-trigger M
Ch n trigger
... ... ... ...
Figure 36-52. Pre-trigger and trigger outputs
The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is
cleared. In this case, when the trigger input event occurs, the pre-trigger m is asserted
after two peripheral clock cycles.
The PDB can be configured in back-to-back operation. Back-to-back operation enables
the ADC conversions complete to trigger the next PDB channel pre-trigger and trigger
outputs, so that the ADC conversions can be triggered on next set of configuration and
results registers. When back-to-back is enabled by setting CHnC1[BB[m]], the delay m is
ignored and the pre-trigger m is asserted two peripheral cycles after the acknowledgment
m is received. The acknowledgment connections in this MCU is described in Back-to-
back acknowledgment connections.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
826
Preliminary
Freescale Semiconductor, Inc.
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