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When an ADC conversion, which is triggered by one of the pre-triggers from PDB
channel n, is in progress and ADCnSC1[COCO] is not set, a new trigger from PDB
channel n pre-trigger m cannot be accepted by ADCn. Therefore every time when one
PDB channel n pre-trigger and trigger output starts an ADC conversion, an internal lock
associated with the corresponding pre-trigger is activated. The lock becomes inactive
when the corresponding ADCnSC1[COCO] is set, or the corresponding PDB pre-trigger
is disabled, or the PDB is disabled. The channel n trigger output is suppressed when any
of the locks of the pre-triggers in channel n is active. If a new pre-trigger m asserts when
there is active lock in the PDB channel n, a register flag bit, CHnS[ERR[m]], associated
with the pre-trigger m is set. If SC[PDBEIE] is set, the sequence error interrupt is
generated. Sequence error is typically happened because the delay m is set too short and
the pre-trigger m asserts before the previously triggered ADC conversion is completed.
When the PDB counter reaches the value set in IDLY register, the SC[PDBIF] flag is set.
A PDB interrupt can be generated if SC[PDBIE] is set and SC[DMAEN] is cleared. If
SC[DMAEN] is set, PDB requests a DMA transfer when SC[PDBIF] is set.
The modulus value in MOD register, is used to reset the counter back to zero at the end
of the count. If SC[CONT] bit is set, the counter will then resume a new count.
Otherwise, the counter operation will cease until the next trigger input event occurs.
36.4.2 PDB trigger input source selection
The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are
connected to on-chip or off-chip event sources. The PDB can be triggered by software
through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or
software trigger.
For the trigger input sources implemented in this MCU, see chip configuration
information.
36.4.3 DAC interval trigger outputs
PDB can generate the interval triggers for DACs to update their outputs periodically.
DAC interval counter x is reset and started when a trigger input event occurs if
DACINTCx[EXT] is cleared. When the interval counter x is equal to the value set in
DACINTx register, the DAC interval trigger x output generates a pulse of one peripheral
clock cycle width to update the DACx. If DACINTCx[EXT] is set, the DAC interval
counter is bypassed and the interval trigger output x generates a pulse following the
detection of a rising edge on the DAC external trigger input. The counter and interval
trigger can be disabled by clearing the DACINTCx[TOE].
Chapter 36 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
827
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