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DAC interval counters are also reset when the PDB counter reaches the MOD register
value; therefore, when the PDB counter rolls over to zero, the DAC interval counters
starts anew.
Together, the DAC interval trigger pulse and the ADC pre-trigger/trigger pulses allow
precise timing of DAC updates and ADC measurements. This is outlined in the typical
use case described in the following diagram.
PDB
counter
MOD, IDLY
0
DACINTx
DACINTx x3
DACINTx x2
... ...
CHnDLY1
CHnDLY0
DAC internal trigger x
Ch n pre-trigger 0
Ch n pre-trigger 1
Ch n trigger
PDB interrupt
... ...
Trigger input event
Figure 36-53. PDB ADC triggers and DAC interval triggers use case
NOTE
Because the DAC interval counters share the prescaler with
PDB counter, PDB must be enabled if the DAC interval trigger
outputs are used in the applications.
36.4.4 Pulse-Out's
PDB can generate pulse outputs of configurable width. When PDB counter reaches the
value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches
POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than
POyDLY[DLY1].
Because the PDB counter is shared by both ADC pre-trigger/trigger outputs and Pulse-
Out generation, they have the same time base.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
828
Preliminary
Freescale Semiconductor, Inc.
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