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The pulse-out connections implemented in this MCU are described in the device's chip
configuration details.
36.4.5 Updating the delay registers
The following registers control the timing of the PDB operation; and in some of the
applications, they may need to become effective at the same time.
• PDB Modulus Register (MOD)
• PDB Interrupt Delay Register (IDLY)
• PDB Channel n Delay m Register (CHnDLYm)
• DAC Interval x Register (DACINTx)
• PDB Pulse-Out y Delay Register (POyDLY)
The internal registers of them are buffered and any values written to them are written first
to their buffers. The circumstances that cause their internal registers to be updated with
the values from the buffers are summarized as shown in the table below.
Table 36-54. Circumstances of update to the delay registers
SC[LDMOD] Update to the delay registers
00 The internal registers are loaded with the values from their
buffers immediately after 1 is written to SC[LDOK].
01 The PDB counter reaches the MOD register value after 1 is
written to SC[LDOK].
10 A trigger input event is detected after 1 is written to
SC[LDOK].
11 Either the PDB counter reaches the MOD register value, or a
trigger input event is detected, after 1 is written to SC[LDOK].
After 1 is written to SC[LDOK], the buffers cannot be written until the values in buffers
are loaded into their internal registers. SC[LDOK] is self-cleared when the internal
registers are loaded, so the application code can read it to determine the updates to the
internal registers.
The following diagrams show the cases of the internal registers being updated with
SC[LDMOD] is 00 and x1.
Chapter 36 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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