Information

PDB Counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CHnDLY1
CHnDLY0
SC[LDOK]
Figure 36-54. Registers Update with SC[LDMOD] = 00
PDB Counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CHnDLY1
CHnDLY0
SC[LDOK]
Figure 36-55. Registers update with SC[LDMOD] = x1
36.4.6 Interrupts
PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The
following table summarizes the interrupts.
Table 36-55. PDB interrupt summary
Interrupt Flags Enable bit
PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and
SC[DMAEN] = 0
PDB Sequence Error Interrupt CHnS[ERRm] SC[PDBEIE] = 1
36.4.7 DMA
If SC[DMAEN] is set, PDB can generate DMA transfer request when SC[PDBIF] is set.
When DMA is enabled, the PDB interrupt will not be issued.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
830
Preliminary
Freescale Semiconductor, Inc.
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