Information

FTM memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_8058 Synchronization (FTM0_SYNC) 32 R/W 0000_0000h
37.3.11/
854
4003_805C Initial State For Channels Output (FTM0_OUTINIT) 32 R/W 0000_0000h
37.3.12/
857
4003_8060 Output Mask (FTM0_OUTMASK) 32 R/W 0000_0000h
37.3.13/
858
4003_8064 Function For Linked Channels (FTM0_COMBINE) 32 R/W 0000_0000h
37.3.14/
860
4003_8068 Deadtime Insertion Control (FTM0_DEADTIME) 32 R/W 0000_0000h
37.3.15/
865
4003_806C FTM External Trigger (FTM0_EXTTRIG) 32 R/W 0000_0000h
37.3.16/
866
4003_8070 Channels Polarity (FTM0_POL) 32 R/W 0000_0000h
37.3.17/
867
4003_8074 Fault Mode Status (FTM0_FMS) 32 R/W 0000_0000h
37.3.18/
870
4003_8078 Input Capture Filter Control (FTM0_FILTER) 32 R/W 0000_0000h
37.3.19/
872
4003_807C Fault Control (FTM0_FLTCTRL) 32 R/W 0000_0000h
37.3.20/
873
4003_8080 Quadrature Decoder Control And Status (FTM0_QDCTRL) 32 R/W 0000_0000h
37.3.21/
875
4003_8084 Configuration (FTM0_CONF) 32 R/W 0000_0000h
37.3.22/
877
4003_8088 FTM Fault Input Polarity (FTM0_FLTPOL) 32 R/W 0000_0000h
37.3.23/
878
4003_808C Synchronization Configuration (FTM0_SYNCONF) 32 R/W 0000_0000h
37.3.24/
880
4003_8090 FTM Inverting Control (FTM0_INVCTRL) 32 R/W 0000_0000h
37.3.25/
882
4003_8094 FTM Software Output Control (FTM0_SWOCTRL) 32 R/W 0000_0000h
37.3.26/
883
4003_8098 FTM PWM Load (FTM0_PWMLOAD) 32 R/W 0000_0000h
37.3.27/
885
4003_9000 Status And Control (FTM1_SC) 32 R/W 0000_0000h 37.3.3/844
4003_9004 Counter (FTM1_CNT) 32 R/W 0000_0000h 37.3.4/845
4003_9008 Modulo (FTM1_MOD) 32 R/W 0000_0000h 37.3.5/846
4003_900C Channel (n) Status And Control (FTM1_C0SC) 32 R/W 0000_0000h 37.3.6/847
4003_9010 Channel (n) Value (FTM1_C0V) 32 R/W 0000_0000h 37.3.7/849
4003_9014 Channel (n) Status And Control (FTM1_C1SC) 32 R/W 0000_0000h 37.3.6/847
4003_9018 Channel (n) Value (FTM1_C1V) 32 R/W 0000_0000h 37.3.7/849
4003_901C Channel (n) Status And Control (FTM1_C2SC) 32 R/W 0000_0000h 37.3.6/847
4003_9020 Channel (n) Value (FTM1_C2V) 32 R/W 0000_0000h 37.3.7/849
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
840
Preliminary
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