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37.3.6 Channel (n) Status And Control (FTMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function.
Table 37-67. Mode, edge, and level selection
DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X X X XX 0 None Pin not used for
FTM
0 0 0 0 1 Input Capture Capture on
Rising Edge
Only
10 Capture on
Falling Edge
Only
11 Capture on
Rising or Falling
Edge
1 1 Output Compare Toggle Output
on match
10 Clear Output on
match
11 Set Output on
match
1X 10 Edge-Aligned
PWM
High-true pulses
(clear Output on
match)
X1 Low-true pulses
(set Output on
match)
1 XX 10 Center-Aligned
PWM
High-true pulses
(clear Output on
match-up)
X1 Low-true pulses
(set Output on
match-up)
1 0 XX 10 Combine PWM High-true pulses
(set on channel
(n) match, and
clear on channel
(n+1) match)
X1 Low-true pulses
(clear on
channel (n)
match, and set
on channel (n
+1) match)
Table continues on the next page...
Chapter 37 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
847
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