Information

Address: Base address + 10h offset + (8d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CnV field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
VAL
Channel Value
Captured FTM counter value of the input modes or the match value for the output modes
37.3.8 Counter Initial Value (FTMx_CNTIN)
The Counter Initial Value register contains the initial value for the FTM counter.
Writing to the CNTIN register latches the value into a buffer. The CNTIN register is
updated with the value of its write buffer according to Registers updated from write
buffers.
When the FTM clock is initially selected, by writing a non-zero value to the CLKS bits,
the FTM counter starts with the value 0x0000. To avoid this behavior, before the first
write to select the FTM clock, write the new value to the the CNTIN register and then
initialize the FTM counter by writing any value to the CNT register.
Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved INIT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CNTIN field descriptions
Field Description
31–16
Reserved
This field is reserved.
15–0
INIT
Initial Value Of The FTM Counter
37.3.9 Capture And Compare Status (FTMx_STATUS)
The STATUS register contains a copy of the status flag CHnF bit in CnSC for each FTM
channel for software convenience.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
850
Preliminary
Freescale Semiconductor, Inc.
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