Information

37.3.14 Function For Linked Channels (FTMx_COMBINE)
This register contains the control bits used to configure the fault control, synchronization,
deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for
each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6.
Address: Base address + 64h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
FAULTEN3
SYNCEN3
DTEN3
DECAP3
DECAPEN3
COMP3
COMBINE3
0
FAULTEN2
SYNCEN2
DTEN2
DECAP2
DECAPEN2
COMP2
COMBINE2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FAULTEN1
SYNCEN1
DTEN1
DECAP1
DECAPEN1
COMP1
COMBINE1
0
FAULTEN0
SYNCEN0
DTEN0
DECAP0
DECAPEN0
COMP0
COMBINE0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_COMBINE field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
FAULTEN3
Fault Control Enable For n = 6
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
29
SYNCEN3
Synchronization Enable For n = 6
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
28
DTEN3
Deadtime Enable For n = 6
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
860
Preliminary
Freescale Semiconductor, Inc.
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