Information

37.3.18 Fault Mode Status (FTMx_FMS)
This register contains the fault detection flags, write protection enable bit, and the logic
OR of the enabled fault inputs.
Address: Base address + 74h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FAULTF
WPEN
FAULTIN
0
FAULTF3 FAULTF2 FAULTF1 FAULTF0
W
0
0 0 0 0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FMS field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
FAULTF
Fault Detection Flag
Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0. Clear FAULTF by reading the
FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition
at the enabled fault inputs. Writing a 1 to FAULTF has no effect.
If another fault condition is detected in an enabled fault input before the clearing sequence is completed,
the sequence is reset so FAULTF remains set after the clearing sequence is completed for the earlier fault
condition. FAULTF is also cleared when FAULTFj bits are cleared individually.
0 No fault condition was detected.
1 A fault condition was detected.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
870
Preliminary
Freescale Semiconductor, Inc.
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