Information

FTMx_QDCTRL field descriptions (continued)
Field Description
0
QUADEN
Quadrature Decoder Mode Enable
Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM
counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 37-7.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Quadrature Decoder mode is disabled.
1 Quadrature Decoder mode is enabled.
37.3.22 Configuration (FTMx_CONF)
This register selects the number of times that the FTM counter overflow should occur
before the TOF bit to be set, the FTM behavior in BDM modes, the use of an external
global time base, and the global time base signal generation.
Address: Base address + 84h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
GTBEOUT
GTBEEN
0
BDMMODE
0
NUMTOF
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CONF field descriptions
Field Description
31–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
GTBEOUT
Global Time Base Output
Enables the global time base signal generation to other FTMs.
0 A global time base signal generation is disabled.
1
A global time base signal generation is enabled.
9
GTBEEN
Global Time Base Enable
Configures the FTM to use an external global time base signal that is generated by another FTM.
Table continues on the next page...
Chapter 37 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
877
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