Information

FTMx_SYNCONF field descriptions (continued)
Field Description
0 FTM clears the TRIGj bit when the hardware trigger j is detected.
1 FTM does not clear the TRIGj bit when the hardware trigger j is detected.
37.3.25 FTM Inverting Control (FTMx_INVCTRL)
This register controls when the channel (n) output becomes the channel (n+1) output, and
channel (n+1) output becomes the channel (n) output. Each INVmEN bit enables the
inverting operation for the corresponding pair channels m.
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register
synchronization.
Address: Base address + 90h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INV3EN INV2EN INV1EN INV0EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_INVCTRL field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
INV3EN
Pair Channels 3 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
2
INV2EN
Pair Channels 2 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
1
INV1EN
Pair Channels 1 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
882
Preliminary
Freescale Semiconductor, Inc.
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